06 December 2011, 14:11

Kernel Log: Coming in 3.2 (Part 3) - Architecture

by Thorsten Leemhuis

Optimised assembler code paths accelerate SHA1 and speed up the Blowfish and Twofish encryption algorithms. The next scheduled Linux kernel release avoids a cache problem found in AMD's latest processors and includes new and extended drivers for Intel CPUs.

In keeping with the usual weekly release rhythm, Linus Torvalds issued the fourth release candidate of Linux 3.2 last Friday. It contains fewer changes than the two previous RCs, and Torvalds said that "things really are calming down pretty nicely", adding that it is even "suspiciously quiet." With the development of Linux 3.2 in progress, the Kernel Log is continuing its "Coming in 3.2" mini series. After describing the advancements in the kernel's network driver and infrastructure areas and those relating to filesystems, we will now cover the changes relating to the kernel's architecture and processor support; in the coming weeks, further articles will discuss the kernel's infrastructure and drivers.

Optimised encryption and decryption

An additional SHA1 implementation for x86-64 CPUs is designed to allow the hash algorithm to achieve higher throughputs by using SSE3 or AVX commands; according to the developer's measurement results, the implementation increased an IPSec connection's throughput on a Core 2 Quad from 344 to 464 Mbits/s.

The Blowfish code was extended to include an x86-64 assembler implementation, while the Twofish code now offers a 3-way parallel assembler implementation for x86-64 systems. Measurement values listed in the commit comments demonstrate that both implementations considerably speed up these encryption and decryption mechanisms; for example, decrypting with Blowfish was reported to be between two and two-and-a-half times faster in certain cases.

Architecture support

Various patches (for example, 1) allow Linux 3.2 to avoid the effects of an L1 instruction cache peculiarity in AMD's Bulldozer processors that can cause performance losses in certain situations. These patches have also been submitted for the series 3.0 and 3.1 stable kernels (1, 2), but haven't yet been integrated there yet.

Also newly supported is the Ivy Bridge CPUs' random number generator, which can be addressed via the RDRAND x86 instruction; Intel plans to introduce these processors as the successors of its Sandy Bridge components next year (1, 2). The EDAC (Error Detection And Correction) subsystem now includes an experimental new driver for Intel's Sandy Bridge EP processors (1, 2, 3). The i7core_edac driver now offers an interface to set the memory scrub rate.

Linux now supports Qualcomm's Hexagon CPU architecture (for example, 1, 2). Background information on this architecture is available in the article entitled "Upcoming DSP architectures" on LWN.net; the C6X architecture support also mentioned there has not been included in this round, but will probably follow in version 3.3.

Miscellaneous

The clock source driver for Microsoft's Hyper-V virtualisation technology has moved from the staging area to the x86 architecture code. With Microsoft programmers having made numerous improvements, various other drivers for core Hyper-V technologies have also managed to leave the staging directory. The Hyper-V drivers for emulated mouse, network and storage hardware will remain in the staging area for the time being, but will probably move for 3.3.

The developers have continued the ARM code restructuring and clean-up work that has been ongoing for several months. The new Highbank and Picoxcell sub-architectures allow the kernel to address the chip families of the same name. Also new is the kernel's support of the imx6q SoC family (for example, 1, 2), the Denx MX28, and of Omicron ixp425-based boards.

Changes to the code for Power/PowerPC processors include support for the new Power "Non Virtualized" Platform (for example, 1). Some recent systems offer this new operational mode, called PowerNV, in which Linux doesn't run under a hypervisor but virtualises independently via KVM.